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a sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? embedded processor adsp-21261 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bi t floating-point processor code compatibilityat assembly level, uses the same instruction set as other sharc dsps single-instruction multiple-data (simd) computational archi- tecturetwo 32-bit ieee floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, alu, shifter, and register file high bandwidth i/oa parallel port, an spi ? port, four serial ports, a digital applications interface (dai), and jtag dai incorporates two precision clock generators (pcgs), an input data port (idp) that includes a parallel data acquisi- tion port (pdap), and three programmable timers, all under software control by the signal routing unit (sru) on-chip memory1m bit of on-chip sram and a dedicated 3m bit of on-chip mask-programmable rom the adsp-21261 is available in commercial and industrial temperature grades. for complete ordering information, see ordering guide on page 44 . key features serial ports offer left-justified sample-pair and i 2 s support via 12 programmable and simultaneous receive or trans- mit pins, which support up to 24 transmit or 24 receive i 2 s channels of audio when all fo ur serial ports (sports) are enabled or six full duplex tdm streams of up to 128 channels per frame at 150 mhz (6.67 ns) core instruction rate, the adsp-21261 operates at 900 mflops peak/600 mflops sustained per- formance whether operating on fixed- or floating-point data 300 mmacs sustained performance at 150 mhz super harvard architecturethree independent buses for dual data fetch, instruction fetch, and nonintrusive, zero- overhead i/o transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle, sustained 1.8g byte/s bandwidth at 150 mhz core instruction rate and 900m byte/s is available via dma figure 1. function al block diagram addr data px register 6 jtag test & emulation 20 3 se rial ports (4 ) input data ports (8) parallel data acquis ition p ort timers (3) si gnal ro u ti ng unit precisi on clo ck generators (2) digital applications interface 3 16 address/ data bus/gpio control/gpio parallel port iop registers (memory mapped) control, status, data buffers 4 sp i po rt (1) dma controller 18 channels 4 gpio flag s/ irq /timexp processing element (pey) proces sing elem ent (pex) timer instruction cache 32 48 -bit dag1 8 4 32 dag2 8 4 32 32 pm address bus dm address bus pm data bus dm data bus 64 64 core process or program seq ue nce r addr data sram 0.5m bit ro m 1.5 m bit dual ported memory block 0 dual ported memory block 1 s iod (32) ioa (18) 32 i/o processor rom 1. 5m bit sram 0. 5m bit
rev. 0 | page 2 of 44 | march 2006 adsp-21261 additional key features 1m bit on-chip dual-ported sram (0.5m bit block 0, 0.5m bit block 1) for simultaneous access by core processor and dma 3m bit on-chip dual-ported mask-programmable rom (1.5m bit in block 0 and 1.5m bit in block 1) dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping with single-cycle loop setup, providing efficient program sequencing single-instruction, multiple-data (simd) architecture provides: two computational processing elements concurrent executioneach processing element executes the same instruction, but operates on different data parallelism in buses and computational units allows single cycle executions (with or wi thout simd) of a multiply operation; an alu operation; a dual memory read or write; and an instruction fetch accelerated fft butterfly computation through a multiply with add and subtract instruction dma controller supports: 18 zero-overhead dma channels for transfers between the adsp-21261 internal memory and serial ports (eight), the input data port (idp) (eight), the spi-compatible port (one), and the parallel port (one) 32-bit background dma transfers at core clock speed, in parallel with full-speed processor execution jtag background telemetry for enhanced emulation features ieee 1149.1 jtag standard test access port and on-chip emulation dual voltage: 3.3 v i/o, 1.2 v core available in 136-ball bga and 144-lead lqfp packages also available in lead-free packages digital applications interface includes four serial ports, two precision clock generators, an input data port, three pro- grammable timers, and a signal routing unit asynchronous parallel/external port provides: access to asynchronous external memory 16 multiplexed address/data lines that can support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 50m byte/s transfer rate for 150 mhz core rate 256 word page boundaries external memory access in a dedicated dma channel 8-bit to 32-bit and 16-bit to 32-bit word packing options programmable wait state options: 2 to 31 cclk serial ports provide: four dual data line serial ports that operate at up to 37.5m bit/s for a 150 mhz core on each data lineeach has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair left-justified sample-pair and i 2 s support, programmable direction for up to 16 simultaneous receive or transmit channels using two i 2 s-compatible stereo devices per serial port tdm support for telecommunications interfaces including 128 tdm channel support for newer telephony inter- faces such as h.100/h.110 up to 12 tdm stream suppor t, each with 128 channels per frame companding selection on a per channel basis in tdm mode input data port provides an additional input path to the sharc core configurable as either eight channels of i 2 s or serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port supports receive audio channel data in i 2 s, left-justified sample pair, or right-justified mode signal routing unit (sru) provid es configurable and flexible connections between all dai components, four serial ports, two precision clock generators, three timers, an input data port/parallel data acquisition port, 10 inter- rupts, six flag inputs, six flag outputs, and 20 sru i/o pins (dai_px) serial peripheral interface (spi) master or slave serial boot through spi full-duplex operation master-slave mode multimaster support open-drain outputs programmable baud rates, clock polarities, and phases 3 muxed flag/irq lines 1 muxed flag/timer expired line rom-based security features: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios
adsp-21261 rev. 0 | page 3 of 44 | march 2006 table of contents general description ................................................. 4 adsp-21261 family core architecture .. .................... 4 simd computational engine ............................... 4 independent, parallel computation units ................ 4 data register file ............................................... 5 single-cycle fetch of instruction and four operands ............................................... 5 instruction cache .............................................. 5 data address generators with zero-overhead hardware circular buffer support ...................... 5 flexible instruction set ....................................... 6 adsp-21261 memory and i/ o interface features ......... 6 dual-ported on-chip memory ............................. 6 dma controller ................................................ 6 digital applications interface (dai) ....................... 6 serial ports ....................................................... 6 serial peripheral (compatible) interface .................. 7 parallel port ..................................................... 7 timers ............................................................ 8 program booting ............................................... 8 phase-locked loop ............................................ 8 power supplies .................................................. 8 target board jtag emulator connector .................... 8 development tools ............................................... 8 evaluation kit ..................................................... 10 designing an emul ator-compatible dsp board (target) ........................................... 10 additional information ......................................... 10 pin function descriptions ........................................ 11 address data pins as flags ..................................... 14 boot modes ........................................................ 14 core instruction rate to clkin ratio modes ............. 14 address data modes ............................................. 14 adsp-21261 specifications ....................................... 15 recommended operating conditions ....................... 15 electrical characteristics ........................................ 15 absolute maximum ratings ................................... 16 esd sensitivity .................................................... 16 timing specifications ........................................... 17 power-up sequencing ....................................... 18 clock input ..................................................... 19 clock signals ................................................... 19 reset ............................................................. 20 interrupts ....................................................... 20 core timer ..................................................... 20 timer pwm_out cycle timing ......................... 21 timer wdth_cap timing ............................... 21 dai pin-to-pin direct routing ............................ 22 precision clock generator (direct pin routing) ...... 23 flags ............................................................. 24 memory readparallel port ............................... 25 memory writeparallel port ............................. 27 serial ports ..................................................... 29 input data port (idp) ....................................... 32 parallel data acquisition port (pdap) .................. 33 spi protocolmaster ........................................ 34 spi protocolslave .......................................... 34 jtag test access port and emulation .................. 36 output drive currents ......................................... 37 test conditions .................................................. 37 capacitive loading .............................................. 37 environmental conditions .................................... 38 thermal characteristics ........................................ 38 136-ball bga pin configurations ............................... 39 144-lead lqfp pin configurations .. .......................... 42 package dimensions ............................................... 43 surface mount design .......................................... 44 ordering guide ..................................................... 44 revision history 3/06rev. 0: initial release
rev. 0 | page 4 of 44 | march 2006 adsp-21261 general description the adsp-21261 sharc dsp is a member of the simd sharc family of dsps featuring analog devices super har- vard architecture. the adsp-21261 is source code compatible with the adsp-2126x, adsp-21160, and adsp-21161 dsps, as well as with first generation adsp-2106x sharc processors in sisd (single-instruction, single -data) mode. like other sharc dsps, the adsp-21261 is a 32-bit/ 40-bit floating-point proces- sor optimized for high performa nce signal processing applica- tions with its dual-ported on -chip sram, mask-programmable rom, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital applications interface. as shown in the functional block diagram on page 1, the adsp-21261 uses two computational units to deliver a five to 10 times performance increase over previous sharc processors on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, the adsp-21261 dsp achieves an instruction cycle time of 6.67 ns at 150 mhz. with its simd computational ha rdware, the adsp-21261 can perform 900 mflops running at 150 mhz. table 1 shows performance benchm arks for the adsp-21261. the adsp-21261 continues sharc s industry-leading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. the block diagram of the adsp-21261 on page 1 illustrates the following architec tural features: ? two processing elements, each containing an alu, multi- plier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ? three programmable interval timers with pwm genera- tion, pwm capture/pulse width measurement, and external event counter capabilities ? on-chip dual-ported sram (1m bit) ? on-chip dual-ported, mask-programmable rom (3m bit) ? jtag test access port ? 8- or 16-bit parallel port that supports interfaces to off-chip memory peripherals ? dma controller ? four full-duplex serial ports ? spi-compatible interface ? digital applications interface that includes two precision clock generators (pcg), an input data port (idp), four serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three programmable timers, and a flexible signal routing unit (sru) figure 2 shows one sample configur ation of a sport using the precision clock generator to interface with an i 2 s adc and an i 2 s dac with a much lower jitter clock than the serial port would generate itself. many other sru configurations are possible. adsp-21261 family core architecture the adsp-21261 is code compatible at the assembly level with the adsp-2126x, adsp-2136x, ad sp-2116x, and the first gen- eration adsp-2106x sharc ds ps. the adsp-21261 shares architectural features with the adsp-2126x, adsp-2136x, and adsp-2116x simd sharc family of dsps, as detailed in the following sections. simd computational engine the adsp-21261 contains two co mputational processing ele- ments that operate as a single-instruction, multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and reg- ister file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instru ction is executed in both pro- cessing elements, but each proc essing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing table 1. adsp-21261 benchmarks (at 150 mhz) benchmark algorithm speed (at 150 mhz) 1024 point complex fft (radix 4, with reversal) 46 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode. 2.5 ns iir filter (per biquad) 1 10 ns matrix multiply (pipelined) [33] [31] [44] [41] 22.5 ns 40 ns divide (y/) 15 ns inverse square root 22.5 ns
adsp-21261 rev. 0 | page 5 of 44 | march 2006 element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel alu and multiplier operations occur in both processing ele- ments. these computation unit s support ieee 32-bit single precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each processing element. the register files transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the adsp-2126x enhanced har- vard architecture, allow unco nstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. single-cycle fetch of instruction and four operands the adsp-21261 features an enhanc ed harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 1 on page 1 ). with the adsp-21261s separate pro- gram and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruct ion (from the cache), all in a single cycle. instruction cache the adsp-21261 includes an on-c hip instruction cache that enables three-bus operation for fe tching an instruction and four data values. the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators with zero-overhead hardware circular buffer support the adsp-21261s two data addr ess generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are common ly used in digi tal filters and fourier transforms. the two da gs of the adsp-21261 contain sufficient registers to allow the creation of up to 32 circular buff- ers (16 primary register sets , 16 secondary). the dags automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. circular buffers can start and end at any memory location. figure 2. adsp-21261 syst em sample configuration dai sport3 spo rt2 sp ort1 sport0 sclk0 sd0a sfs0 sd0b sru da i_ p1 dai_p2 dai_p3 da i_ p1 8 da i_ p19 da i_p 20 dac (optional) adc (optional) fs clk sdat fs clk sdat 3 clock 2 2 clkin xtal clk_cfg1?0 bootcfg1?0 flag 3?1 addr parallel po rt ra m , r om boot rom i/o device oe da t a we rd wr clkout ale ad15?0 latch rese t jtag 6 adsp-21261 address data control cs fl a g 0 pcgb pcg a clk fs
rev. 0 | page 6 of 44 | march 2006 adsp-21261 flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations for concise prog ramming. for example, the adsp-21261 can conditionally exec ute a multiply, an add, and a subtract in both processing el ements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. adsp-21261 memory and i/o interface features the adsp-21261 adds the following architectural features to the simd sharc family core: dual-ported on-chip memory the adsp-21261 contains one mega bit of internal sram and three megabits of internal mask-programmable rom. each block can be configured for diffe rent combinations of code and data storage (see memory map, figure 3 ). each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o proc essor. the dual-ported memory, in com- bination with three separate on-chip buses, allows two data transfers from the core and one fr om the i/o processor, in a sin- gle cycle. the adsp-21261s sram can be co nfigured as a maximum of 48k words of 32-bit data, 46k words of 16-bit data, 31.5k words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to one megabi t. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit float- ing-point storage format is suppo rted that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one dedicated to each memory block, assures single-c ycle execution with two data transfers. in this case, the in struction must be available in the cache. dma controller the adsp-21261s on-chip dma co ntroller allows zero-over- head data transfers without pr ocessor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simul- taneously executing its progra m instructions. dma transfers can occur between the adsp-21261 s internal memory and its serial ports, the spi-compatible (serial peripheral interface) port, the idp (input data port), parallel data acquisition port (pdap), or the parallel port. ei ghteen channels of dma are available on the adsp-21261one for the spi, eight via the serial ports, eight via the input data port, and one via the proces- sors parallel port. programs ca n be downloaded to the adsp- 21261 using dma transfers. other dma features include inter- rupt generation upon completion of dma transfers, and dma chaining for automatic linked dma transfers. digital applications interface (dai) the digital applications interface provides the ability to connect various peripherals to any of the sharcs dai pins (dai_p20C1). connections are made using th e signal routing unit (sru, shown in the block diagram on page 1 ). the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. th is allows easy use of the dai associated peripherals for a much wider variety of applications by using a larger set of algorith ms than is possible with noncon- figurable signal paths. the dai also includes four serial ports, two precision clock gen- erators (pcgs), an input data po rt (idp), six flag outputs and six flag inputs, and three timers. the idp provides an additional input path to the adsp-21261 core, configurable as either eight channels of i 2 s or serial data, or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. each data channel has its own dma channel that is independent from the adsp-21261s serial ports. for complete information on using the dai, see the adsp-2126x sharc dsp peripherals manual . serial ports the adsp-21261 features four fu ll-duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the analog devices ad183x family of audi o codecs, adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has its own dedicated dma channel. serial ports are enabled via eight programmable and simulta- neous receive or transmit pins that support up to 18 transmit or 18 receive channels of serial data when all six sports are enabled, or four full-duplex tdm streams of 128 channels per frame. the serial ports operate at up to one-quarter of the dsp core clock rate, providing each wi th a maximum data rate of 37.5m bit/s for a 150 mhz core. seri al port data can be auto- matically transferred to and from on-chip memory via a dedicated dma. each of the serial ports can work in conjunc- tion with another serial port to provide tdm support. one sport provides two transmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in four modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ? left-justified sa mple pair mode
adsp-21261 rev. 0 | page 7 of 44 | march 2006 serial peripheral (compatible) interface serial peripheral interface is an industry-standard synchronous serial link, enabling the adsp -21261 spi-compatible port to communicate with other spi-comp atible devices. spi is an interface consisting of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, supporting both master and sl ave modes. the spi port can operate in a multimaster environment by interfacing with up to four other spi-compatible devices, either acting as a master or slave device. the adsp-21261 sp i-compatible peripheral implementation also features programmable baud rates up to 37.5 mhz, clock phases, and polarities. the adsp-21261 spi- compatible port uses open-drain drivers to support a multimas- ter configuration and to avoid data contention. parallel port the parallel port provides interf aces to sram and peripheral devices. the multiplexed address and data pins (ad15C0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of ad dress. in either mode, 8- or 16- bit, the maximum data transfer rate is one-third the core clock speed. as an example, a clock rate of 200 mhz is equivalent to 66m byte/s, and a clock rate of 150 mhz is equivalent to 50m byte/s. figure 3. adsp-21261 memory map reserved 0x0004 2000?0x0005 7fff block 0 rom (1.5m bit) 0x0005 8000?0x0002 ffff iop registers 0x0000 0000?0x0003 ffff block 0 sram (0.5m bit) 0x0004 0000?0x0004 1fff reserved 0x0005 3000?0x0005 ffff block 1 sram (0.5m bit) 0x0006 0000?0x0006 1fff block 1 rom (1.5m bit) 0x0007 8000?0x0007 dfff reserved 0x0007 e000?0x0007 ffff reserved 0x0006 2000?0x0007 7fff long word addressing reserved 0x0008 4000 - 0x000a ffff block 0 rom (1.5m bit) 2 0x000b 0000?0x000b bfff iop registers 0x0000 0000?0x0003 ffff block 0 sram (0.5m bit) 0x0008 0000?0x0008 3fff reserved 0x000b c000?0x000b ffff block 1 sram (0.5m bit) 0x000c 0000?0x000c 3fff block 1 rom (1.5m bit) 3 0x000f 0000?0x000f bfff reserved 0x000f c000?0x000f ffff reserved 0x000c 4000?0x000e ffff normal word addressing reserved 0x0010 8000?0x0015 ffff block 0 rom (1.5m bit) 0x0016 0000?0x0017 7fff iop registers 0x0000 0000?0x0003 ffff block 0 sram (0.5m bit) 0x0010 0000?0x0010 7fff reserved 0x0017 8fff?0x0017 ffff block 1 sram (0.5m bit) 0x0018 0000?0x0018 7fff block 1 rom (1.5m bit) 0x001e 0000?0x001f 7fff reserved 0x0018 8000?0x001d ffff short word addressing reserved 0x0020 0000?0x00ff ffff external dma address space 1 0x0100 0000?0x02ff ffff reserved 0x0300 0000?0x3fff ffff external memory space 1 external memory is not directly accessible by the core. dma must be used to read or write to this memo ry using the spi or parallel port. 2 block 0 rom has a 48-bit address range (0xa0000?0xa7 ffff). 3 block 1 rom has a 48-bit address range (0xe0000?0xe7 ffff). internal memory space reserved 0x000
rev. 0 | page 8 of 44 | march 2006 adsp-21261 dma transfers are used to move data to and from internal memory. access to the core is also facilitated through the paral- lel port register read/write functions. the rd , wr , and ale (address latch enable) pins are the control pins for the parallel port. timers the adsp-21261 has a total of four timers: a core timer able to generate periodic software interrupts, and three general- purpose timers that can generate periodic interrupts and be independently set to operat e in one of three modes: ? pulse waveform generation mode ? pulse width count/capture mode ? external event watchdog mode the core timer can be configur ed to use flag3 as a timer expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32- bit pulse width register. a sin- gle control and status register enables or disables all three general-purpose timers independently. program booting the internal memory of th e adsp-21261 boots at system power-up from an 8- bit eprom via the parallel port, an spi master, an spi slave, or an inte rnal boot. booting is determined by the boot configuration (bootc fg1C0) pins. selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin executing from rom. phase-locked loop the adsp-21261 uses an on-chip phase-locked loop (pll) to generate the internal clock for the core. on power-up, the clkcfg1 C 0 pins are used to select ratios of 16:1, 8:1, and 3:1. after booting, numerous other ra tios can be selected via soft- ware control. the ratios are made up of software configurable numerator values from 1 to 32 an d software configurable divi- sor values of 1, 2, 4, 8, and 16. power supplies the adsp-21261 has separate po wer supply connections for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.2 v requirement. th e external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same power supply. note that the analog supply pin (a vdd ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the a vdd pin. place the filter componen ts as close as possible to the a vdd /a vss pins. for an example circuit, see figure 4 . (a recom- mended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pcb should use a parallel pair of power and ground planes for v ddint and gnd. use wide traces to connect the bypass capacitors to the analog power (a vdd ) and ground (a vss ) pins. note that the a vdd and a vss pins specified in figure 4 are inputs to the proc essor and not the analog ground plane on the boardthe a vss pin should connect directly to digital ground (gnd) at the chip. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test acce ss port of the adsp-21261 pro- cessor to monitor and control the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces- sor stacks. the processors jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools the adsp-21261 is supported by a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and visualdsp++ ? ? development environment. the sa me emulator hardware that supports other sharc processors also fully emulates the adsp-21261. the visualdsp++ project manage ment environment lets pro- grammers develop and debug an application. this environment includes an easy to use assemble r (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instru ction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the adsp-21261 sharc dsp has architectural features that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enha nced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in figure 4. analog power filter circuit ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc. hi z ferrite bead chip locate all components close to a vdd and a vss pins a vdd a vss 100nf 10nf 1nf adsp-21261 v ddint
adsp-21261 rev. 0 | page 9 of 44 | march 2006 complexity, this capability can ha ve increasing significance on the designers development schedule, increasing productivity. statistical profiling enables the programmer to nonintrusively poll the processor as it is runn ing the program. this feature, unique to visualdsp++, enables the software developer to pas- sively gather important code execution metrics without interrupting the real-time characte ristics of the program. essen- tially, the developer can identify bottlenecks in software quickly and efficiently. by using the pr ofiler, the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and ma nage all of the sharc devel- opment tools, including the color syntax highlighting in the visualdsp++ editor. this capabi lity permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gen- eration of various vdk-based objects, and visualizing the system state, when debugging an application that uses the vdk. visualdsp++ component softwa re engineering (vcse) is analog devices technology fo r creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reli ably assemble so ftware applica- tions. it also is used for do wnloading components from the web, dropping them into the a pplication, and publishing com- ponent archives from within visualdsp++. vcse supports component implementation in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the dsp or external memory with a drag of the mouse, and examine runtime stack and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the develo per to move between the graphi- cal and textual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc processor pc plug-in cards. third- party software tools include dsp libraries, real-time operating systems, and block diagram design tools.
rev. 0 | page 10 of 44 | march 2006 adsp-21261 evaluation kit analog devices offers a range of ez-kit lite ? ? evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping applic ations with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board alon g with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample application progra ms, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-k it lite board connects the board to the usb port of the users pc, enabling the visu- aldsp++ evaluation suite to emul ate the on-board processor in- circuit. this permit s the customer to download, execute, and debug programs for the ez-kit li te system. it also allows in- circuit programming of the on-board flash device to store user- specific boot code, enabling the board to run as a standalone unit, without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom-defined system. connecting an analog devices jtag emulator to the ez-kit lite bo ard enables high speed, nonin- trusive emulation. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supp lied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in-circuit emulation is assured by the use of the processors jtag inter- facethe emulator does not affe ct target syst em loading or timing. the emulator uses the tap to access the internal fea- tures of the dsp, allowing th e developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halt ed to send data and commands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on sys- tem timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvem ents to emulator support. additional information this data sheet provides a ge neral overview of the adsp-21261 architecture and functionality. for detailed information on the adsp-2126x family core architectu re and instruction set, refer to the adsp-2126x dsp core manual and the adsp-21160 sharc dsp instruction set reference . ? ez-kit lite is a registered trademark of analog devices, inc.
adsp-21261 rev. 0 | page 11 of 44 | march 2006 pin function descriptions adsp-21261 pin definitions are list ed below. inputs identified as synchronous (s) must meet ti ming requirements with respect to clkin (or with respect to tc k for tms, tdi). inputs iden- tified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for the following: ? dai_px, spiclk, miso, mosi, emu , tms,trst , tdi, and ad15C0 (note: these pins have internal pull-up resistors.) the following symbol s appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state. table 2. pin function descriptions pin type state during and after reset function ad15C0 i/o/t ad15C0 pins are driven low both during and after reset parallel port address/data. the adsp-21261 parallel port and its corresponding dma unit output addresses and data for pe ripherals on these multiplexed pins. the multiplex state is determined by the ale pi n. the parallel port can operate in either 8-bit or 16-bit mode. each ad pin has a 22.5 k internal pull-up resistor. see address data modes on page 14 for details of the ad pin operation. for 8-bit mode: ale is automatically asse rted whenever a change occurs in the upper 16 external address bits, a23C8; ale is used in conjunction with an external latch to retain the values of the a23C8. for 16-bit mode: ale is automatically asserted whenever a change occurs in the address bits, a15C0; ale is used in conjunct ion with an external latch to retain the values of the a15C0. to use these pins as flags (flag15C0) set (=1) bit 20 of the sysctl register and disable the parallel port. see table 3 on page 14 for a list of how the ad15C0 pins map to the flag pins. when configured in the idp_pdap_ctl register, the idp channel 0 can use these pins for parallel input data. rd o output only, driven high 1 parallel port read enable. rd is asserted low whenever the dsp reads 8-bit or 16-bit data from an external memory device. when ad15C0 are flags, this pin remains deasserted. wr o output only, driven high 1 parallel port write enable. wr is asserted low whenever the dsp writes 8-bit or 16-bit data to an external memory device. when ad15C0 are flags, this pin remains deasserted. ale o output only, driven low 1 parallel port address latch enable. ale is asserted whenever the dsp drives a new address on the parallel port address pin. on reset, ale is active high. however, it can be reconfigured using software to be active low. when ad15C0 are flags, this pin remains deasserted. flag3C0 i/o/a three-state flag pins. each flag pin is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. these pins can be used as an spi slave select output during spi mastering. these pins are also multiplexed with the irqx and the timexp signals. in spi master boot mode, flag0 is the slave select pin that must be connected to an spi eprom. flag0 is configured as a slave select during spi master boot. when bit 16 is set (=1) in the sysctl register, flag0 is configured as irq0 . when bit 17 is set (=1) in the sysctl register, flag1 is configured as irq1 . when bit 18 is set (=1) in the sysctl register, flag2 is configured as irq2 . when bit 19 is set (=1) in the sysctl regi ster, flag3 is configured as timexp, which indicates that the system timer has expired.
rev. 0 | page 12 of 44 | march 2006 adsp-21261 dai_p20C1 i/o/t three-state with programmable pull-up digital applications interface pins . these pins provide the physical interface to the sru. the sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. the configuration registers of these peripherals then determine the exact behavior of the pin. any input or output signal pr esent in the sru may be routed to any of these pins. the sru provides the connection from the serial ports, input data port, precision clock generators, and timers to the dai_p20C1 pins. these pins have internal 22.5 k pull-up resistors which are enabled on reset. these pull-ups can be disabled in the dai_pin_pullup register. spiclk i/o three-state with pull-up enabled serial peripheral interface clock signal . driven by the master, this signal controls the rate at which data is tr ansferred. the master can transmit data at a variety of baud rates. spiclk cycles once for each bi t transmitted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices ignore the serial clock if the slave select input is driven inactive (high). spiclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. spiclk has a 22.5 k internal pull-up resistor. if spi master boot mode is selected, mosi and spiclk pins are driven during reset. these pins are not three-stated during reset in spi master boot mode. spids i input only serial peripheral interface slave device select . an active low signal used to select the dsp as an spi slave device. this input si gnal behaves like a chip select, and is provided by the master device for the slave devices. in multimaster mode the dsps spids signal can be driven by a slave device to signal to the dsp (as spi master) that an error has occurred, as some other device is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multimaster error. for a single master, multiple-slave co nfiguration where flag pins are used, this pin must be tied or pulled high to v ddext on the master device. for adsp-21261 to adsp-21261 spi interaction, any of the master adsp-21261s flag pins can be used to drive the spids signal on the adsp-21261 spi slave device. mosi i/o (o/d) three-state with pull-up enabled spi master out slave in . if the adsp-21261 is configured as a master, the mosi pin becomes a data transmit (output) pin, tr ansmitting output data. if the adsp-21261 is configured as a slave, the mosi pin beco mes a data receive (i nput) pin, receiving input data. in an adsp-21261 spi interconne ction, the data is shifted out from the mosi output pin of the master and shifted into the mosi input(s) of the slave(s). mosi has a 22.5 k internal pull-up resistor. if spi master boot mode is selected, mosi and spiclk pins are driven during reset. these pins are not three-stated during reset in spi master boot mode. miso i/o (o/d) three-state with pull-up enabled spi master in slave out . if the adsp-21261 is configured as a master, the miso pin becomes a data receive (input) pin, receiving input data. if the adsp-21261 is configured as a slave, the miso pin become s a data transmit (output) pin, trans- mitting output data. in an adsp-21261 spi interconnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. miso has a 22.5 k internal pull-up resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note: only one slave is allowed to transmit data at any given time. to enable broadcast transmission to multiple spi slaves, the ds ps miso pin may be disabled by setting (=1) bit 5 (dmiso) of the spictl register. bootcfg1C0 i input only boot configuration select . selects the boot mode for the dsp. the bootcfg pins must be valid before reset is asserted. see table 4 on page 14 for a description of the boot modes. table 2. pin function descriptions (continued) pin type state during and after reset function
adsp-21261 rev. 0 | page 13 of 44 | march 2006 clkin i input only local clock in . used in conjunction with xtal. cl kin is the adsp-21261 clock input. it configures the adsp-21261 to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the adsp-21261 to use the external clock source such as an external clock oscillator. the core is clocked either by the pll output or this clock input depending on the clkcfg1C0 pin settings. clkin may not be halted, changed, or operated below the specified frequency. xtal o output only 2 crystal oscillator terminal . used in conjunction with clkin to drive an external crystal. clkcfg1C0 i input only core/clkin ratio control . these pins set the start-up clock frequency. see table 5 for a description of the cl ock configuration modes. note that the operating frequency can be changed by programming the pll multi- plier and divider in the pmctl register at any time after the core comes out of reset. rstout /clkout o output only reset out/local clock out . drives out the core reset signal to an external device. clkout can also be configured as a reset out pin (rstout ). the functionality can be switched between the pll output clock an d reset out by setting bit 12 of the pmctl register. the default is reset out. reset i/a input only processor reset . resets the adsp-21261 to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i input only 3 test clock (jtag) . provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held lo w for proper operation of the adsp-21261. tms i/s three-state with pull-up enabled test mode select (jtag) . used to control the test state machine. tms has a 22.5 k internal pull-up resistor. tdi i/s three-state with pull-up enabled test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 22.5 k internal pull-up resistor. tdo o three-state 4 test data output (jtag) . serial scan output of the boundary scan path. trst i/a three-state with pull-up enabled test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21261. trst has a 22.5 k internal pull-up resistor. emu o (o/d) three-state with pull-up enabled emulation status . must be connected to the analog devices dsp tools product line of jtag emulators target board connector only. emu has a 22.5 k internal pull- up resistor. v ddint p core power supply . nominally +1.2 v dc and supplies the dsps core processor (13 pins on the bga package, 32 pins on the lqfp package). v ddext p i/o power supply . nominally +3.3 v dc (6 pins on the bga package, 10 pins on the lqfp package). a vdd p analog power supply . nominally +1.2 v dc and supp lies the dsps internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 8. a vss g analog power supply return . gnd g power supply return . (54 pins on the bga package, 39 pins on the lqfp package). 1 rd , wr , and ale are continuously driven by the dsp and will not be three-stated. 2 output only is a three-state driver wi th its output path always enabled. 3 input only is a three-state driver, with both output path and pull-up disabled. 4 three-state is a three-state driver, with pull-up disabled. table 2. pin function descriptions (continued) pin type state during and after reset function
rev. 0 | page 14 of 44 | march 2006 adsp-21261 address data pins as flags to use these pins as flags (flag15C0) set (=1) bit 20 of the sysctl register and di sable the parallel port. boot modes core instruction rate to clkin ratio modes address data modes table 6 shows the functionality of the ad pins for 8-bit and 16-bit transfers to the parallel port . for 8-bit data transfers, ale latches address bits a23Ca8 when asserted, followed by address bits a7Ca0 and data bits d7Cd 0 when deasserted. for 16-bit data transfers, ale latches addr ess bits a15Ca0 when asserted, followed by data bits d15Cd0 when deasserted. table 3. ad15C0 to flag pin mapping ad pin flag pin ad0 flag8 ad1 flag9 ad2 flag10 ad3 flag11 ad4 flag12 ad5 flag13 ad6 flag14 ad7 flag15 ad8 flag0 ad9 flag1 ad10 flag2 ad11 flag3 ad12 flag4 ad13 flag5 ad14 flag6 ad15 flag7 table 4. boot mode selection bootcfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 parallel port boot via eprom 11 internal boot mode (rom code only) table 5. core instruction rate/clkin ratio selection clkcfg1C0 core to clkin ratio 00 3:1 01 16:1 10 8:1 11 reserved table 6. address/data mode selection ep data mode ale ad7C0 function ad15C8 function 8-bit asserted a15C8 a23C16 8-bit deasserted d7C0 a7C0 16-bit asserted a7C0 a15C8 16-bit deasserted d7C0 d15C8
adsp-21261 rev. 0 | page 15 of 44 | march 2006 adsp-21261 specifications recommended operating conditions electrical characteristics parameter 1 1 specifications subject to change without notice. min max unit v ddint internal (core) supply voltage 1.14 1.26 v a vdd analog (pll) supply voltage 1.14 1.26 v v ddext external (i/o) supply voltage 3.13 3.47 v v ih high level input voltage 2 @ v ddext = max 2 applies to input and bid irectional pins: ad15C0, flag3C0, dai_px, spiclk, mosi, miso, spids , bootcfgx, clkcfgx, reset , tck, tms, tdi, and trst . 2.0 v ddext + 0.5 v v il low level input voltage 2 @ v ddext = min C0.5 +0.8 v v ih_clkin high level input voltage 3 @ v ddext = max 3 applies to input pin clkin. 1.74 v ddext + 0.5 v v il_clkin low level input voltage @ v ddext = min C0.5 +1.19 v t amb ambient operating temperature 4, 5 4 see thermal characteristics on page 38 for information on th ermal specifications. 5 see engineer-to-engineer note (no. 216) for further information. 0+70 c parameter 1 test conditions min max unit v oh high level output voltage 2 @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol low level output voltage 2 @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih high level input current 4, 5 @ v ddext = max, v in = v ddext max 10 a i il low level input current 4 @ v ddext = max, v in = 0 v 10 a i ilpu low level input current pull-up 5 @ v ddext = max, v in = 0 v 200 a i ozh three-state leakage current 6, 7, 8 @ v ddext = max, v in = v ddext max 10 a i ozl three-state leakage current 6 @ v ddext = max, v in = 0 v 10 a i ozlpu three-state leakage current pull-up 7 @ v ddext = max, v in = 0 v 200 a i dd-intyp supply current (internal) 9, 10, 11 t cclk = 6.67 ns, v ddint = 1.2 v, t amb = +25 c375ma ai dd supply current (analog) 11 a vdd = max 10 ma c in input capacitance 12, 13 f in = 1 mhz, t case = 25c, v in = 1.2 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidir ectional pins: ad15C0, rd , wr , ale, flag3C0, dai_px, spiclk, mosi, miso, emu , tdo, clkout, and xtal. 3 see output drive currents on page 37 for typical drive current capabilities. 4 applies to input pins: spids , bootcfgx, clkcfgx, tck, reset , and clkin. 5 applies to input pins with 22.5 k internal pull-ups: trst , tms, and tdi. 6 applies to three-statable pins: flag3C0. 7 applies to three-statable pins with 22.5 k pull-ups: ad15C0, dai_px, spiclk, miso, and mosi. 8 applies to open-drain output pins: emu , miso, and mosi. 9 typical internal current data reflec ts nominal operating conditions. 10 see engineer-to-engineer note (no. 216) for further information. 11 characterized, but not tested. 12 applies to all signal pins. 13 guaranteed, but not tested.
rev. 0 | page 16 of 44 | march 2006 adsp-21261 absolute maximum ratings esd sensitivity parameter rating internal (core) supply voltage (v ddint ) 1 1 stresses greater than those listed ab ove may cause permane nt damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. C0.3 v to +1.4 v analog (pll) supply voltage (a vdd ) 1 C0.3 v to +1.4 v external (i/o) supply voltage (v ddext ) 1 C0.3 v to +3.8 v input voltage C0.5 v to v ddext 1 +0.5 v output voltage swing C0.5 v to v ddext 1 +0.5 v load capacitance 1 200 pf storage temperature range 1 C65 c to +150 c junction temperature under bias 125 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21261 features proprietary esd protec tion circuitry, perman ent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance de gradation or loss of functionality.
adsp-21261 rev. 0 | page 17 of 44 | march 2006 timing specifications the adsp-21261s internal clock (a multiple of clkin) pro- vides the clock signal for timi ng internal memory, processor core, serial ports, and parallel po rt (as required for read/write strobes in asynchrono us access mode). during reset, program the ratio between the dsps internal clock frequency and exter- nal (clkin) clock frequency with the clkcfg1C0 pins. to determine switching frequencies for the serial ports, divide down the internal clock, usin g the programmable divider con- trol of each port (divx for the serial ports). the adsp-21261s intern al clock switches at higher frequencies than the system input clock (clk in). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsps internal clock (the clock source for the parallel po rt logic and i/o pads). note the definitions of various clock periods that are a function of clkin and the appropriate ratio control ( table 7 and table 8 ). figure 5 shows core to clkin ratios of 3:1, 8:1, and 16:1 with external oscillator or crystal. no te that more ratios are possible and can be set through software using the power management control register (pmctl). for more information, see the adsp-2126x sharc dsp core manual . use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or su btraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 30 on page 37 under test conditions for voltage reference levels. switching characteristics specif y how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to si gnals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. table 7. adsp-21261 clkout and cclk clock generation operation timing requirements description calculation clkin input clock 1/t ck cclk core clock 1/t cclk table 8. clock periods timing requirements description 1 1 where: sr = serial port-to-core clock ra tio (wide range, determined by sport clkdiv) spir = spi-to-core clock ratio (wid e range, determined by spibaud register) dai_px = serial port clock spiclk = spi clock t ck clkin clock period t cclk (processor) core clock period t sclk serial port clock period = (t cclk ) sr t spiclk spi clock period = (t cclk ) spir figure 5. core clock and system clock relationship to clkin clkin cclk (core clock) plliclk xtal xtal osc pll 3:1, 8:1, 16:1 clkout clkcfg1?0
rev. 0 | page 18 of 44 | march 2006 adsp-21261 power-up sequencing the timing requirements fo r dsp startup are given in table 9 and figure 6 . table 9. power-up sequencing (dsp startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd clkin valid after v ddint /v ddext valid 1 0200ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 3 s switching characteristic t corerst dsp core reset deasserted after reset deasserted 4096t ck 4, 5 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. voltage ramp rates can vary from microseconds to h undreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. re fer to the crystal oscillator manufacturers data sheet fo r startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin an d internal oscillator circuit in conjunction with an external c rystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subsequent resets require a minimum of four clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 11 . if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 6. power-up sequencing clkin reset t rstvdd rstout v ddext v ddint t pllrst t clkrst t clkvdd t ivddevdd clkcfg1?0 t corerst multiplexed with clkout * *
adsp-21261 rev. 0 | page 19 of 44 | march 2006 clock input see table 10 and figure 7 . clock signals the adsp-21261 can use an external clock or a crystal. see clkin pin description. the pr ogrammer can configure the adsp-21261 to use its internal clock generator by connecting the necessary components to clkin and xtal. figure 8 shows the component connections used for a crystal operating in fun- damental mode. note that the 150 mhz clock rate is achieved using a 9.375 mhz crystal and a pll multiplier ratio 16:1 (cclk:clkin). table 10. clock input parameter min max unit timing requirements t ck clkin period 20 1 160 2 ns t ckl clkin width low 7.5 1 80 2 ns t ckh clkin width high 7.5 1 80 2 ns t ckrf clkin rise/fall (0.4 vC2.0 v) 3 ns t cclk cclk period 3 6.66 10 ns 1 applies only for clkcfg1 C 0 = 00 and default values for pll control bits in pmctl. 2 applies only for clkcfg1 C 0 = 01 and default values for pll control bits in pmctl. 3 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . figure 7. clock input figure 8. 150 mhz operation with a 9.375 mhz fundamental mode crystal clkin t ck t ckh t ckl clkin xtal c1 c2 x1 note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. crystal selection must comply with clkcfg1?0 = 10 or = 01. 1m
rev. 0 | page 20 of 44 | march 2006 adsp-21261 reset see table 11 and figure 9 . interrupts the timing specification in table 12 and figure 10 applies to the flag0, flag1, and flag2 pins when they are configured as irq0 , irq1 , and irq2 interrupts. also applies to dai_p20C1 pins when configured as interrupts. core timer the timing specification in table 13 and figure 11 applies to flag3 when it is configured as the core timer (ctimer). table 11. reset parameter min max unit timing requirements t wrst reset pulse width low 1 4t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the processors internal ph ase-locked loop requires no more than 1 00 s while reset is low, assuming stable vdd and clkin (not including start-up time of external clock oscillator). figure 9. reset clkin reset t wrst t srst table 12. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t cclk +2 ns figure 10. interrupts dai_p20?1 (flag2?0) (irq2C0) t ipw table 13. core timer parameter min max unit switching characteristic t wctim ctimer pulse width 4 t cclk C 1 ns figure 11. core timer flag3 (ctimer) t wctim
adsp-21261 rev. 0 | page 21 of 44 | march 2006 timer pwm_out cycle timing the timing specification in table 14 and figure 12 applies to timer pwm_out (pulse-width modulation) mode. timer sig- nals are routed to the dai_p20C1 pins through the sru. therefore, the timing specificatio ns provided below are valid at the dai_p20C1 pins. timer wdth_cap timing the timing specification in table 15 and figure 13 applies to timer wdth_cap (pulse widt h count and capture) mode. timer signals are routed to the dai_p20C1 pins through the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 14. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t cclk C 1 2(2 31 C 1) t cclk ns figure 12. timer pwm_out timing dai_p20?1 (timer) t pwmo table 15. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t cclk 2(2 31 C 1) t cclk ns figure 13. timer width capture timing dai_p20?1 (timer) t pwi
rev. 0 | page 22 of 44 | march 2006 adsp-21261 dai pin-to-pin direct routing see table 16 and figure 14 for direct pin connections only (for example dai_pb01_i to dai_pb02_o). table 16. dai pin-to-pin direct routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 10 ns figure 14. dai pin-to-pin direct routing dai_pn t dpio dai_pm
adsp-21261 rev. 0 | page 23 of 44 | march 2006 precision clock generator (direct pin routing) the timing in table 17 and figure 15 is valid only when the sru is configured such that the precision clock generator (pcg) takes its inputs directly fr om the dai pins (via pin buff- ers) and sends its outputs directly to the dai pins. for the other cases where the pcgs inputs and outputs are not directly routed to/from dai pins (via pi n buffers) there is no timing data available. all timing parameters and switching characteris- tics apply to external dai pins (dai_p07 C dai_p20). table 17. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgiw input clock pulse width 20 ns t strig pcg trigger setup before falling edge of pcg input clock 2 ns t htrig pcg trigger hold after falling edge of pcg input clock 2 ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock falling edge 2.5 10 ns t dtrig pcg output clock and frame sync delay after pcg trigger 2.5 + 2.5 t pcgow 10 + 2.5 t pcgow ns t pcgow output clock pulse width 40 ns figure 15. precision clock generator (direct pin routing) dai_pn pcg_trigx_i t strig dai_pm pcg_extx_i (clkin) dai_py pcg_clkx_o dai_pz pcg_fsx_o t htrig t dpcgio t dtrig t pcgow t pcgiw
rev. 0 | page 24 of 44 | march 2006 adsp-21261 flags the timing specifications in table 18 and figure 16 apply to the flag3C0 and dai_p20C1 pins, the parallel port, and the serial peripheral interface. see table 2 on page 11 for more informa- tion on flag use. table 18. flags parameter min max unit timing requirement t fipw flag3C0 in pulse width 2 t cclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t cclk C 1 ns figure 16. flags dai_p20?1 (flag3?0 in ) (ad15?0) dai_p20?1 (flag3?0 out ) (ad15?0) t fopw t fipw
adsp-21261 rev. 0 | page 25 of 44 | march 2006 memory readparallel port the specifications in table 19 , table 20 , figure 17 , and figure 18 are for asynchronous interfacing to memories (and memory-mapped peripherals) wh en the adsp-21261 is access- ing external memory space. table 19. 8-bit memory read cycle parameter min max unit timing requirements t drs address/data7C0 setup before rd high 3.3 ns t drh address/data7C0 hold after rd high 0 ns t dad address 15C8 to data valid d + 0.5 t cclk C 3.5 ns switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data15C0 setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data15C0 hold after ale deasserted 1 0.5 t cclk C 0.8 ns t alehz ale deasserted 1 to address/data7C0 in high z 0.5 t cclk C 0.8 0.5 t cclk + 2.0 ns t rw rd pulse width d C 2 ns t adrh address/data15C8 hold after rd high 0.5 t cclk C 1 + h ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by software to be active low. figure 17. 8-bit memory read cycle valid data ad15?8 valid address valid address t adas valid address ad7?0 t alew ale rd t rw wr t adah t adrh t alehz t drs t drh t dad t alerw
rev. 0 | page 26 of 44 | march 2006 adsp-21261 table 20. 16-bit memory read cycle parameter min max unit timing requirements t drs address/data15C0 setup before rd high 3.3 ns t drh address/data15C0 hold after rd high 0 ns switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data15C0 setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data15C0 hold after ale deaserted 1 0.5 t cclk C 0.8 ns t alehz ale deasserted 1 to address/data15C0 in high z 0.5 t cclk C 0.8 0.5t cclk + 2.0 ns t rw rd pulse width d C 2 ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by so ftware to be active low. figure 18. 16-bit memory read cycle valid address valid data t adas t adah ad15?0 t alehz t drs t drh t alew ale rd t rw wr t alerw
adsp-21261 rev. 0 | page 27 of 44 | march 2006 memory writeparallel port use the specifications in table 21 , table 22 , figure 19 , and figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) wh en the adsp-21261 is access- ing external memory space. table 21. 8-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data15C0 setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data15C0 hold after ale deasserted 1 0.5 t cclk C 0.8 ns t ww wr pulse width d C 2 ns t adwl address/data15C8 to wr low 0.5 t cclk C 1.5 ns t adwh address/data15C8 hold after wr high 0.5 t cclk C 1 + h ns t alehz ale deasserted 1 to address/data15C0 in high z 0.5 t cclk C 0.8 0.5t cclk + 2.0 ns t dws address/data7C0 setup before wr high d ns t dwh address/data7C0 hold after wr high 0.5 t cclk C 1.5 + h ns t dawh address/data to wr high d ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by software to be active low. figure 19. 8-bit memory write cycle ad15?8 valid address valid address t adas ad7?0 t alew ale rd t ww wr t adah t adwh t adwl t alehz valid data t dws t dwh valid address t dawh t alerw
rev. 0 | page 28 of 44 | march 2006 adsp-21261 table 22. 16-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t cclk C 2 ns t alerw ale deasserted to read/write asserted 1 t cclk C 0.5 ns t adas address/data 15C0 setup before ale deasserted 1 2.5 t cclk C 2.0 ns t adah address/data15C0 hold after ale deasserted 1 0.5 t cclk C 0.8 ns t ww wr pulse width d C 2 ns t aleh ale deasserted 1 to address/data15C0 in high z 0.5 t cclk C 0.8 0.5t cclk + 2.0 ns t dws address/data15C0 setup before wr high d ns t dwh address/data15C0 hold after wr high 0.5 t cclk C 1.5 + h ns d = (data cycle duration) t cclk h = t cclk (if a hold cycle is specified, else h = 0) 1 on reset, ale is an active high cycle. however, it can be reconfigured by so ftware to be active low. figure 20. 16-bit memory write cycle valid address valid data t adas ad15?0 t alew ale wr t ww rd t adah t dwh t dws t alerw t aleh
adsp-21261 rev. 0 | page 29 of 44 | march 2006 serial ports to determine whether communication is possible between two devices at clock speed n, the specifications in table 23 , table 24 , table 25 , table 26 , figure 21 , and figure 22 must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) sclk width. serial port signals (sclk, fs , dxa,/dxb) are routed to the dai_p20C1 pins using the sru. th erefore, the timing specifica- tions provided below are valid at the dai_p20C1 pins. table 23. serial portsexternal clock parameter min max unit timing requirements t sfse fs setup before sclk (externally generated fs in either transmit or receive mode) 1 2.5 ns t hfse fs hold after sclk (externally generated fs in either transmit or receive mode) 1 2.5 ns t sdre receive data setup before receive sclk 1 2.5 ns t hdre receive data hold after sclk 1 2.5 ns t sclkw sclk width 7 ns t sclk sclk period 20 ns switching characteristics t dfse fs delay after sclk (internally generated fs in either transmit or receive mode) 2 7ns t hofse fs hold after sclk (internally generated fs in either transmit or receive mode) 2 2ns t ddte transmit data delay after transmit sclk 2 7ns t hdte transmit data hold after transmit sclk 2 2ns 1 referenced to sample edge. 2 referenced to drive edge. table 24. serial portsinternal clock parameter min max unit timing requirements t sfsi fs setup before sclk (externally generated fs in either transmit or receive mode) 1 6ns t hfsi fs hold after sclk (externally generated fs in either transmit or receive mode) 1 1.5 ns t sdri receive data setup before sclk 1 6ns t hdri receive data hold after sclk 1 1.5 ns switching characteristics t dfsi fs delay after sclk (internally generated fs in transmit mode) 2 3ns t hofsi fs hold after sclk (internally generated fs in transmit mode) 2 C1.0 ns t dfsi fs delay after sclk (internally generated fs in receive mode) 2 3ns t hofsi fs hold after sclk (internally generated fs in receive mode) 2 C1.0 ns t ddti transmit data delay after sclk 2 3ns t hdti transmit data hold after sclk 2 C1.0 ns t sclkiw transmit or receive sclk width 0.5t sclk C 2 0.5t sclk + 2 ns 1 referenced to the sample edge. 2 referenced to drive edge.
rev. 0 | page 30 of 44 | march 2006 adsp-21261 table 25. serial portsenable and three-state parameter min max unit switching characteristics t ddten data enable from external transmit sclk 1 2ns t ddtte data disable from external transmit sclk 1 7ns t ddtin data enable from internal transmit sclk 1 C1 ns 1 referenced to drive edge. table 26. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 1 7ns t ddtenfs data enable for mce = 1, mfd = 0 1 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justified sample pair mode as well as dsp serial mode, and mce = 1, mfd = 0. figure 21. external late frame sync 1 1 this figure reflects changes made to su pport left-justified sample pair mode. drive sample drive dai_p20?1 (sclk) dai_p20?1 (fs) dai_p20?1 (data channel a/b) drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit dai_p20?1 (sclk) dai_p20?1 (fs) 1st bit 2nd bit t hfse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dai_p20?1 (data channel a/b) note: serial port signals (sclk, fs, data channel a/b ) are routed to the dai_p[20:1] pins using the sru. the timing specifications provided here are valid at the dai_p[20:1] pins. t hfse/i
adsp-21261 rev. 0 | page 31 of 44 | march 2006 figure 22. serial ports drive edge dai_p20?1 sclk (int) drive edge drive edge sclk dai_p20?1 sclk (ext) t ddtte t ddten t ddtin dai_p20?1 (data channel a/b) dai_p20?1 (data channel a/b) dai_p20?1 (sclk) dai_p20?1 (fs) drive edge sample edge data r e c e iv e ?int e rnal clock data r e c e iv e ? e x t e rnal clock drive edge sample edge note: either the rising edge or falling edge of sclk (external) or sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsi t hofsi t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dai_p20?1 (data channel a/b) t ddti drive edge sample edge data transmit?internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw t hdti note: either the rising edge or falling edge of sclk (external) or sclk (internal) can be used as the active sampling edge. t ddte drive edge sample edge data transmit?external clock t sfse t hfse t dfse t hofse t sclkw t hdte dai_p20?1 (sclk) dai_p20?1 (fs) dai_p20?1 (data channel a/b) dai_p20?1 (sclk) dai_p20?1 (fs) dai_p20?1 (data channel a/b) dai_p20?1 (sclk) dai_p20?1 (fs) dai_p20?1 (data channel a/b)
rev. 0 | page 32 of 44 | march 2006 adsp-21261 input data port (idp) the timing requirements for the idp are given in table 27 and figure 23 . idp signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifica- tions provided below are valid at the dai_p20C1 pins. table 27. input data port (idp) parameter min max unit timing requirements t sisfs fs setup before sclk rising edge 1 2.5 ns t sihfs fs hold after sclk rising edge 1 2.5 ns t sisd sdata setup before sclk rising edge 1 2.5 ns t sihd sdata hold after sclk rising edge 1 2.5 ns t idpclkw clock width 7 ns t idpclk clock period 20 ns 1 data, sclk, and fs can come from any of the dai pins. sclk and fs can also come via the precis ion clock generators (pcg) or sp orts. pcg input can be either clkin or any of the dai pins. figure 23. input data port (idp) dai_p20 ? 1 (sclk) dai_p20 ? 1 (fs) sample edge t sisd t sihd t sisfs t sihfs t idpclkw dai_p20 ? 1 (sdata) t idpclk
adsp-21261 rev. 0 | page 33 of 44 | march 2006 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 28 and figure 24 . pdap is the parallel mode operation of channel 0 of the idp. for details on the operation of the idp, see the idp chapter of the adsp-2126x peripherals manual . note that the most significant 16 bits of external pdap data can be provided through either the parallel port ad15C0 or the dai_p20C5 pins. the remaining fo ur bits can only be sourced through dai_p4C1. the timing below is valid at the dai_p20C1 pins or at the ad15C0 pins. table 28. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken pdap_clken setup before pdap_clk sample edge 1 2.5 ns t hpclken pdap_clken hold after pdap_clk sample edge 1 2.5 ns t pdsd pdap_dat setup before sclk pdap_clk sample edge 1 2.5 ns t pdhd pdap_dat hold after sclk pdap_clk sample edge 1 2.5 ns t pdclkw clock width 7 ns t pdclk clock period 20 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t cclk ns t pdstrb pdap strobe pulse width 1 t cclk C 1 ns 1 source pins of data are addr7C0, data7C0, or dai pins. source pins for sclk and fs are: 1) dai pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 24. parallel data acquisition port (pdap) dai_p20?1 (pdap_clk) sample edge t pdsd t pdhd t spclken t hpclken t pdclkw data dai_p20?1 (pdap_clken) t pdstrb t pdhldd dai_p20?1 (pdap_strobe) t pdclk
rev. 0 | page 34 of 44 | march 2006 adsp-21261 spi protocolmaster spi protocolslave see table 30 and figure 26 . table 29. spi protocolmaster parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 5 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t cclk ns t spichm serial clock high period 4 t cclk C 2 ns t spiclm serial clock low period 4 t cclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 3 ns t hdspidm spiclk edge to data out not valid (data out hold time) 10 ns t sdscim flag3C0 out (spi device select) low to first spiclk edge 4 t cclk C 2 ns t hdsm last spiclk edge to flag3C0 out high 4 t cclk C 1 ns t spitdm sequential transfer delay 4 t cclk C 1 ns figure 25. spi protocolmaster lsb valid msb valid t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) flag3?0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase = 1 cphase = 0 t sdscim t sspidm
adsp-21261 rev. 0 | page 35 of 44 | march 2006 table 30. spi protocolslave parameter min max unit timing requirements t spiclks serial clock cycle 4 t cclk ns t spichs serial clock high period 2 t cclk C 2 ns t spicls serial clock low period 2 t cclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t cclk + 1 2 t cclk + 1 ns ns t hds last spiclk edge to spids not asserted cphase = 0 2 t cclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t cclk ns switching characteristics t dsoe spids assertion to data out active 0 5 ns t dsdhi spids deassertion to data high impedance 0 5 ns t ddspids spiclk edge to data out valid (data out delay time) 7.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t cclk C 2 ns t dsov spids assertion to data out valid (cphase = 0) 5 t cclk + 2 ns figure 26. spi protocolslave t hspids t ddspids t dsdhi lsb msb msb valid t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) t sdsco t spichs t spicls t spicls t spiclks t hds t spichs t sspids t hspids t dsdhi lsb valid msb msb valid t dsoe t ddspids miso (output) mosi (input) t sspids lsb valid lsb cphase = 1 cphase = 0 t sdppw t dsov t hdspids
rev. 0 | page 36 of 44 | march 2006 adsp-21261 jtag test access port and emulation see table 31 and figure 27 . table 31. jtag test access port and emulation parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck high 1 7ns t hsys system inputs hold after tck high 1 8ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys system outputs delay after tck low 2 10 ns 1 system inputs = ad15C0, spids , clkcfg1C0, reset , bootcfg1C0 , miso, mosi, spiclk, dai_px, and flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, ad15C0, rd , wr , flag3C0, clkout, emu , and ale. figure 27. jtag test ac cess port and emulation tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21261 rev. 0 | page 37 of 44 | march 2006 output drive currents figure 28 shows typical i-v characteri stics for the output driv- ers of the adsp-21261. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 9 on page 18 through table 31 on page 36 . these include output disable time, output enable time, and capacitive loading. timing is measured on signals wh en they cross the 1.5 v level as described in figure 30 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 29 ). figure 33 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 31 , figure 32 , and figure 33 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20%C80%, v = min) vs. load capacitance. figure 28. adsp-21261 typical drive figure 29. equivalent device loading for ac measurements (includes all fixtures) figure 30. voltage reference levels for ac measurements sweep (v ddext ) voltage (v) ?20 03.5 0.5 1.0 1.5 2 2.5 3.0 0 ?40 ?30 20 40 ?10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3.11v, 70c 3.3v, 25c 3.47v, 0c v oh 30 10 3.11v, 70c 3.3v, 25c 3.47v, 0c 1.5v 30pf to output pin 50 input or output 1.5v 1.5v figure 31. typical output rise/fall time (20% to 80%, v ddext = max) figure 32. typical output rise/fall time (20% to 80%, v ddext = min) load capacitance (pf) 8 0 0 120 40 100 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) y = 0.0722x + 1.4042 80 60 20 rise fall y = 0.0904x + 1.9426 load capacitance (pf) 12 0120 20 40 60 80 100 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 y = 0.0915x + 2.2207 y = 0.0728x +1.6336 rise fall
rev. 0 | page 38 of 44 | march 2006 adsp-21261 environmental conditions the adsp-21261 processor is rate d for performance over the commercial temperature range, t amb = 0c to 70c. thermal characteristics table 32 and table 33 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies wi th jesd51-8. th e junction-to- case measurement complies wi th mil-std-883. all measure- ments use a 2s2p jedec test board. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature (c) t case = case temperature (c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter = typical value from the tables below p d = power dissipation. see ee note no. ee-216 values of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approxi- mation of t j by the equation: where: t a = ambient temperature (c) values of jc are provided for package comparison and pcb design considerations when an external heat sink is required. figure 33. typical output delay or hold vs. load capacitance (at ambient temperature) load capacitance (pf) 7 0120 20 40 60 80 100 5 6 4 o u t p u t d e l a y o r h o l d ( n s ) 3 ? 4 y = 0.0904x - 2.712 2 0 1 ? 1 ? 2 ? 3 t j t case j t pd () + = t j t a ja pd () + = table 32. thermal characteristics for 136-ball bga 1 1 the thermal characteristics values provid ed in this table are modeled values. parameter condition typical unit ja airflow = 0 m/s 31.0 c/w jma airflow = 1 m/s 27.3 c/w jma airflow = 2 m/s 26.0 c/w jc 6.99 c/w jt airflow = 0 m/s 0.16 c/w jmt airflow = 1 m/s 0.30 c/w jmt airflow = 2 m/s 0.35 c/w table 33. thermal characteristics for 144-lead lqfp 1 1 the thermal characteristics values provid ed in this table are modeled values. parameter condition typical unit ja airflow = 0 m/s 32.5 c/w jma airflow = 1 m/s 28.9 c/w jma airflow = 2 m/s 27.8 c/w jc 7.8 c/w jt airflow = 0 m/s 0.5 c/w jmt airflow = 1 m/s 0.8 c/w jmt airflow = 2 m/s 1.0 c/w
adsp-21261 rev. 0 | page 39 of 44 | march 2006 136-ball bga pin configurations table 34 shows the adsp-21261s pin names and their default function after reset (in parentheses). figure 34 on page 41 shows the bga packag e pin assignments. table 34. 136-ball bga pin assignments pin name ball no. pin name ball no. pin name ball no. pin name ball no. clkcfg0 a01 clkcfg1 b01 bootcfg1 c01 v ddint d01 xtal a02 gnd b02 bootcfg0 c02 gnd d02 tms a03 v ddext b03 gnd c03 gnd d04 tck a04 clkin b04 gnd c12 gnd d05 tdi a05 trst b05 gnd c13 gnd d06 clkout a06 a vss b06 v ddint c14 gnd d09 tdo a07 a vdd b07 gnd d10 emu a08 v ddext b08 gnd d11 mosi a09 spiclk b09 gnd d13 miso a10 reset b10 v ddint d14 spids a11 v ddint b11 v ddint a12 gnd b12 gnd a13 gnd b13 gnd a14 gnd b14 v ddint e01 flag1 f01 ad7 g01 ad6 h01 gnd e02 flag0 f02 v ddint g02 v ddext h02 gnd e04 gnd f04 v ddext g13 dai_p18 (sd5b) h13 gnd e05 gnd f05 dai_p19 (sclk45) g14 dai_p17 (sd5a) h14 gnd e06 gnd f06 gnd e09 gnd f09 gnd e10 gnd f10 gnd e11 gnd f11 gnd e13 flag2 f13 flag3 e14 dai_p20 (sfs45) f14
rev. 0 | page 40 of 44 | march 2006 adsp-21261 ad5 j01 ad3 k01 ad2 l01 ad0 m01 ad4 j02 v ddint k02 ad1 l02 wr m02 gnd j04 gnd k04 gnd l04 gnd m03 gnd j05 gnd k05 gnd l05 gnd m12 gnd j06 gnd k06 gnd l06 dai_p12 (sd3b) m13 gnd j09 gnd k09 gnd l09 dai_p13 (sclk23) m14 gnd j10 gnd k10 gnd l10 gnd j11 gnd k11 gnd l11 v ddint j13 gnd k13 gnd l13 dai_p16 (sd4b) j14 dai_p15 (sd4a) k14 dai_p14 (sfs23) l14 ad15 n01 ad14 p01 ale n02 ad13 p02 rd n03 ad12 p03 v ddint n04 ad11 p04 v ddext n05 ad10 p05 ad8 n06 ad9 p06 v ddint n07 dai_p1 (sd0a) p07 dai_p2 (sd0b) n08 dai_p3 (sclk0) p08 v ddext n09 dai_p5 (sd1a) p09 dai_p4 (sfs0) n10 dai_p6 (sd1b) p10 v ddint n11 dai_p7 (sclk1) p11 v ddint n12 dai_p8 (sfs1) p12 gnd n13 dai_p9 (sd2a) p13 dai_p10 (sd2b) n14 dai_p11 (sd3a) p14 table 34. 136-ball bga pin assignments (continued) pin name ball no. pin name ball no. pin name ball no. pin name ball no.
adsp-21261 rev. 0 | page 41 of 44 | march 2006 figure 34. 136-ball bga pin assignments (bottom view, summary) a vss v ddint v ddext i/o signals a vdd gnd use the center block of ground pins to provide thermal pathways to your printed circuit board?s ground plane. key 1 2 3 4 5 6 7 8 9 10 11 12 14 13 p n m l k j h g f e d c b a *
rev. 0 | page 42 of 44 | march 2006 adsp-21261 144-lead lqfp pin configurations table 35 shows the adsp-21261s pin names and their default function after reset (in parentheses). table 35. 144-lead lqfp pin assignments pin name lqfp pin no. pin name lqfp pin no. pin name lqfp pin no. pin name lqfp pin no. v ddint 1v ddint 37 v ddext 73 gnd 109 clkcfg0 2 gnd 38 gnd 74 v ddint 110 clkcfg1 3 rd 39 v ddint 75 gnd 111 bootcfg0 4 ale 40 gnd 76 v ddint 112 bootcfg1 5 ad15 41 dai_p10 (sd2b) 77 gnd 113 gnd 6 ad14 42 dai_p11 (sd3a) 78 v ddint 114 v ddext 7 ad13 43 dai_p12 (sd3b) 79 gnd 115 gnd 8 gnd 44 dai_p13 (sclk23) 80 v ddext 116 v ddint 9v ddext 45 dai_p14 (sfs23) 81 gnd 117 gnd 10 ad12 46 dai_p15 (sd4a) 82 v ddint 118 v ddint 11 v ddint 47 v ddint 83 gnd 119 gnd 12 gnd 48 gnd 84 v ddint 120 v ddint 13 ad11 49 gnd 85 reset 121 gnd 14 ad10 50 dai_p16 (sd4b) 86 spids 122 flag0 15 ad9 51 dai_p17 (sd5a) 87 gnd 123 flag1 16 ad8 52 dai_p18 (sd5b) 88 v ddint 124 ad7 17 dai_p1 (sd0a) 53 dai_p19 (sclk45) 89 spiclk 125 gnd 18 v ddint 54 v ddint 90 miso 126 v ddint 19 gnd 55 gnd 91 mosi 127 gnd 20 dai_p2 (sd0b) 56 gnd 92 gnd 128 v ddext 21 dai_p3 (sclk0) 57 v ddext 93 v ddint 129 gnd 22 gnd 58 dai_p20 (sfs45) 94 v ddext 130 v ddint 23 v ddext 59 gnd 95 a vdd 131 ad6 24 v ddint 60 v ddint 96 a vss 132 ad5 25 gnd 61 flag2 97 gnd 133 ad4 26 dai_p4 (sfs0) 62 flag3 98 clkout 134 v ddint 27 dai_p5 (sd1a) 63 v ddint 99 emu 135 gnd 28 dai_p6 (sd1b) 64 gnd 100 tdo 136 ad3 29 dai_p7 (sclk1) 65 v ddint 101 tdi 137 ad2 30 v ddint 66 gnd 102 trst 138 v ddext 31 gnd 67 v ddint 103 tck 139 gnd 32 v ddint 68 gnd 104 tms 140 ad1 33 gnd 69 v ddint 105 gnd 141 ad0 34 dai_p8 (sfs1) 70 gnd 106 clkin 142 wr 35 dai_p9 (sd2a) 71 v ddint 107 xtal 143 v ddint 36 v ddint 72 v ddint 108 v ddext 144
adsp-21261 rev. 0 | page 43 of 44 | march 2006 package dimensions the adsp-21261 is available in a 136-ball bga package and a 144-lead lqfp package shown in figure 35 and figure 36 . figure 35. 136-ball mini-bga [csp_bga] (bc-136-3) figure 36. 144-lead lqfp (st-144-2) seating plane 0.25 min detail a 0.50 0.45 0.40 (ball diameter) detail a 1.70 max 1. dimensions are in milimeters (mm). 2. the actual position of the ball grid is within 0.15 mm of its ideal position relative to the package edges. 3. compliant to jedec standard mo-205-ae, except for the ball diameter. 4. center dimensions are nominal. a b c d e f g h j k l m n p 10987654321 13 14 11 12 0.80 bsc typ 10.40 bsc sq pin a1 indicator bottom view top view 12.00 bsc sq 0.12 max (ball coplanarity) 0.80 bsc typ 0.80 bsc typ seating plane 1.60 max 0.15 0.05 0.08 max (lead coplanarity) 1.45 1.40 1.35 0.27 0.22 0.17 typ 0.50 bsc typ (lead pitch) 1 36 37 73 72 108 144 109 top view (pins down) 22.00 bsc sq 20.00 bsc sq detail a detail a pin 1 indicator 0.75 0.60 typ 0.45 1. dimensions are in millimeters and comply with jedec standard ms-026-bfb. 2. actual position of each lead is within 0.08 of its ideal position when measured in the lateral direction. 3. center dimensions are nominal.
rev. 0 | page 44 of 44 | march 2006 adsp-21261 ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04932-0-3/06(0) surface mount design table 36 is provided as an aid to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface mount design and land pattern standard . ordering guide table 36. bga data for use with surface mount design package ball attach type solder mask opening ball pad size 136-ball mini-bga (bc-136-3) solder mask defined 0.40 mm diameter 0.53 mm diameter model temperature range 1 1 ranges shown represent ambient temperature. instruction rate on-chip sram rom operating voltage package description package option ADSP-21261SKBC-150 0 c to +70 c 150 mhz 1m bit 3m bit 1.2 v internal 3.3 v external 136-ball bga bc-136-3 adsp-21261skbcz150 2 2 z = pb-free part. 0 c to +70 c 150 mhz 1m bit 3m bit 1.2 v internal 3.3 v external 136-ball bga bc-136-3 adsp-21261skstz150 2 0 c to +70 c 150 mhz 1m bit 3m bit 1.2 v internal 3.3 v external 144-lead lqfp st-144-2

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